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Lecroy數字示波器 WR6100

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產品簡介

Lecroy數字示波器 WR6100

詳細介紹

名稱:數字示波器 WR6100
廠家:Lecroy
型號:WR6100

Vertical System

WR 6030 WR 6050 WR 6051 WR 6100 WR 6200
Nominal Analog Bandwidth @ 50Ω (-3 dB) 350 MHz 500 MHz 500 MHz 1 GHz 2 GHz
Rise Time (Typical) 1 ns 750 ps 750 ps 400 ps 255 ps
Input Channels 4 4 2 4 4
Bandwidth Limiters 25 MHz; 200 MHz
Input Impedance 1MΩ||<20pF (10 MΩ || 9.5pF using PP007 probe)
Input Coupling 50Ω:DC, 1MΩ:AC, DC, GND
Maximum Input Voltage 50 Ω:5 V rms, 1MΩ:250 V max (DC+Peak AC(DC-10 kHz))
Channel-Channel Isolation > 40dB @ <100MHz (3dB @ full bandwidth)
Vertical Resolution 8 bits; up to 11 bits with enhanced resolution (ERES)
Sensitivity
DC Gain Accuracy ?.0 % of Full Scale (typical); ?/font>1.5% full scale (warranted)
Offset Range 50Ω:?00 mV @2-4.95 mV/div, ?1 V @ 5-100 mV/div,
? 10 V @ 102mV - 1 V/div
1MΩ:?00 mV @2-4.95 mV/div, ?1 V @ 5-100 mV/div,
?10 V @ 102mV - 1 V/div, ?100 V @ 1.02-10 V/div
Offset Accuracy ?1.5 % + 0.5 % of offset value + 1 mV)
Probing System BNC or ProBus
Horizontal System
Timebases Internal timebase common to all input channels; an external clock may be applied at the Auxiliary Input
Time/Division Range Real Time: 200 ps/div - 10 s/div, RIS mode: to 20ps, Roll mode: up to 1000 s/div
Clock Accuracy ? 5 ppm @ 25oc (? 10ppm @ 5-40oC)
Jitter Noise Floor 2 ps rms (Typical)
Time Interval Accuracy Clock Accuracy + Jitter Noise Floor
Sample Rate + Delay Time Accuracy Equal to Clock Accuracy
Trigger & Interpolator Jitter (RMS) ≤ 3 ps rms (Typical)
Channel- Channel Deskew Range ? 9x time/div setting, 100 ms max, each channel
External Sample Clock DC to 1 GHz; 50Ω or 1MΩ BNC input
Roll Mode Minimum rise time and amplitude requirements apply at low frequencies. (User selectable. Available at slower time/div settings)
Acquisition System
WR 6030 WR 6050 WR 6051 WR 6100 WR 6200
Single-Shot Sample Rate/Ch 2.5 GS/s 5 GS/s 5 GS/s 5 GS/s 5 GS/s
Interleaved Sample Rate (2Ch) 5 GS/s N/A N/A 10 GS/s 10 GS/s
Max. Random Interleaved Sampling (RIS) Rate <<< 200 GS/s >>>
Max. Trigger Rate 125,000 waveforms/second
Sequence Time Stamp Resolution 1 ns
Minimum Time Between Sequential Segments 8 祍
Acquisition Memory
Standard
Max. acquisition points (4 Ch/2 Ch; 2Ch/1 Ch in 6051)
2M (1Ch)
Option S 2M / 4M
Option M 4M / 8M
Option L 8M / 16M
Option VL 12M / 24M
Acquisition Processing
Time Resolution (min. Single-shot) 200 ps (5 GS/s) for WR6030, WR6050 and WR6051;
100 ps (10GS/s) for WR6100 and WR6200
Averaging Summed and Continuous Averaging to 1 million sweeps
Enhanced Resolution (ERES) From 8.5 to 11 bits vertical resolution
Envelope (Extrema) Envelope, floor or roof for up to 1 million sweeps
Interpolation Linear, Sin/x
Triggering System
Trigger Modes Normal, Auto, Single, and Stop
Sources Any input channel, External, Ext/10, or line; slope and level unique to each source
Trigger Coupling DC
Pre-trigger Delay 0 ? 99% of memory size (adjustable in 1% increments, or 100 ns)
Post-trigger Delay 10,000 divisions in real time mode, limited at slower time/div settings in roll mode)
Hold-off 2 ns to 20 s or 1 to 99,999,999 events
Internal Trigger Level Range ?.1 div from center
Max Trigger Frequency
Trigger Sensitivity with edge trigger (CH1-4+external)
For WR6030 2 div at < 350 MHz
1 div at < 250 MHz
For WR6050 &
WR 6051
2 div at < 500 MHz
1 div at < 350 MHz
For WR6100 2 div at < 1 GHz
1 div at < 750 MHz
For WR6200 2 div at < 2 GHz
1 div at < 1.8 GHz
Trigger Sensitivity with Smart trigger (CH1-4+external)
For WR6030 350 MHz Max
@ ≥ 10 mV
For WR6050 &
WR 6051
500 MHz Max
@ ≥ 10 mV
For WR6100 750 MHz Max
@ ≥ 10 mV
For WR6200 750 MHz Max
@ ≥ 10 mV
Trigger Level DC Accuracy ?4% full scale ? 2 mV (typical)
External Trigger Range EXT/10 ? 4V; EXT ?400mV
Basic Triggers
Edge/Slope/Line Triggers when signal meets slope (positive or negative) and level condition.
SMART Triggers
State or Edge Qualified Triggers on any input source only if a defined state or edge occurred on another input source. Delay
between sources is selectable by time or events.
Dropout Triggers if signal drops out for longer than selected time between 2 ns and 20 s.
Pattern Logic combination (AND, NAND, OR, NOR) of 5 inputs (4 channels and external trigger input, 2 channels and external trigger input (6051))
Each source can be high, low, or don抰 care. The High and Low level can be selected independently.
Triggers at start or end of the pattern.


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